Package Info

verilator


Compiling Verilog HDL simulator


Productivity/Scientific/Electronics

Verilator compiles synthesizable Verilog (not test-bench code), plus some PSL, SystemVerilog and Synthesis assertions into an optimized model which is in turn wrapped inside a C++/SystemC module for faster execution.


License: Artistic-2.0 or LGPL-3.0
URL: https://www.veripool.org/projects/verilator/wiki/Intro

Categories

Releases

Package Version Update ID Released Package Hub Version Platforms Subpackages
3.900-bp150.2.4 info GA Release 2018-07-30 15
  • ppc64le
  • s390x
  • x86-64
  • verilator
  • verilator-doc
  • verilator-doc-pdf
  • verilator-examples
3.900-bp150.2.5 info GA Release 2018-07-31 15
  • AArch64
  • verilator
  • verilator-doc
  • verilator-doc-pdf
  • verilator-examples
3.900-bp151.2.11 info GA Release 2019-05-18 15 SP1
  • ppc64le
  • verilator
  • verilator-doc
  • verilator-doc-pdf
  • verilator-examples
3.900-bp151.3.1 info GA Release 2019-07-17 15 SP1
  • AArch64
  • s390x
  • x86-64
  • verilator
  • verilator-doc
  • verilator-doc-pdf
  • verilator-examples
3.900-bp152.3.14 info GA Release 2020-04-17 15 SP2
  • AArch64
  • ppc64le
  • s390x
  • x86-64
  • verilator
  • verilator-doc
  • verilator-doc-pdf
  • verilator-examples
3.900-bp153.1.15 info GA Release 2021-03-06 15 SP3
  • AArch64
  • ppc64le
  • s390x
  • x86-64
  • verilator
  • verilator-doc
  • verilator-doc-pdf
  • verilator-examples