Verilator compiles synthesizable Verilog (not test-bench code), plus some PSL, SystemVerilog and Synthesis assertions into an optimized model which is in turn wrapped inside a C++/SystemC module for faster execution.
| Package Version | Update ID | Released | Package Hub Version | Platforms | Subpackages |
|---|---|---|---|---|---|
| 3.900-bp156.3.5 info | GA Release | 2024-05-13 | 15 SP6 |
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| 3.900-bp155.2.11 info | GA Release | 2023-05-22 | 15 SP5 |
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| 3.900-bp154.1.21 info | GA Release | 2022-05-09 | 15 SP4 |
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| 3.900-bp153.1.15 info | GA Release | 2021-03-06 | 15 SP3 |
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| 3.900-bp152.3.14 info | GA Release | 2020-04-17 | 15 SP2 |
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| 3.900-bp151.3.1 info | GA Release | 2019-07-17 | 15 SP1 |
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| 3.900-bp151.2.11 info | GA Release | 2019-05-18 | 15 SP1 |
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| 3.900-bp150.2.5 info | GA Release | 2018-07-31 | 15 |
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| 3.900-bp150.2.4 info | GA Release | 2018-07-30 | 15 |
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