This update for binutils fixes the following issues:

Update to current 2.43.1 branch [jsc#PED-10474]:

Update to version 2.43: 

* new .base64 pseudo-op, allowing base64 encoded data as strings
* Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF
  (APX_F now fully supported)
* x86 Intel syntax now warns about more mnemonic suffixes
* macros and .irp/.irpc/.rept bodies can use \+ to get at number
  of times the macro/body was executed
* aarch64: support 'armv9.5-a' for -march, add support for LUT
  and LUT2
* s390: base register operand in D(X,B) and D(L,B) can now be
  omitted (ala 'D(X,)'); warn when register type doesn't match
  operand type (use option
  'warn-regtype-mismatch=[strict|relaxed|no]' to adjust)
* riscv: support various extensions: Zacas, Zcmp, Zfbfmin,
  Zvfbfmin, Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw,
  XSfCease, all at version 1.0;
  remove support for assembly of privileged spec 1.9.1 (linking
  support remains)
* arm: remove support for some old co-processors: Maverick and FPA
* mips: '--trap' now causes either trap or breakpoint instructions
  to be emitted as per current ISA, instead of always using trap
  insn and failing when current ISA was incompatible with that
* LoongArch: accept .option pseudo-op for fine-grained control
  of assembly code options; add support for DT_RELR
* readelf: now displays RELR relocations in full detail;
  add -j/--display-section to show just those section(s) content
  according to their type
* objdump/readelf now dump also .eh_frame_hdr (when present) when
  dumping .eh_frame
* gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake
  processors; add minimal support for riscv
* linker:
  - put .got and .got.plt into relro segment
  - add -z isa-level-report=[none|all|needed|used] to the x86 ELF
    linker to report needed and used x86-64 ISA levels
  - add --rosegment option which changes the -z separate-code
    option so that only one read-only segment is created (instead
    of two)
  - add --section-ordering-file <FILE> option to add extra
    mapping of input sections to output sections
  - add -plugin-save-temps to store plugin intermediate files
    permanently

Update to version 2.42:

* Add support for many aarch64 extensions: SVE2.1, SME2.1, B16B16,
  RASv2, LSE128, GCS, CHK, SPECRES2, LRCPC3, THE, ITE, D128, XS and
  flags to enable them: '+fcma', '+jscvt', '+frintts', '+flagm2',
  '+rcpc2' and '+wfxt'
* Add experimantal support for GAS to synthesize call-frame-info for
  some hand-written asm (--scfi=experimental) on x86-64.
* Add support for more x86-64 extensions: APX: 32 GPRs, NDD, PUSH2/POP2,
  PUSHP/POPP; USER_MSR, AVX10.1, PBNDKB, SM4, SM3, SHA512, AVX-VNNI-INT16.
* Add support for more RISC-V extensions: T-Head v2.3.0, CORE-V v1.0,
  SiFive VCIX v1.0.
* BPF assembler: ';' separates statements now, and does not introduce
  line comments anymore (use '#' or '//' for this).
* x86-64 ld: Add '-z mark-plt/-z nomark-plt' to mark PLT entries with
  dynamic tags.
* risc-v ld: Add '--[no-]check-uleb128'.
* New linker script directive: REVERSE, to be combined with SORT_BY_NAME
  or SORT_BY_INIT_PRIORITY, reverses the generated order.
* New linker options --warn-execstack-objects (warn only about execstack
  when input object files request it), and --error-execstack plus
  --error-rxw-segments to convert the existing warnings into errors.
* objdump: Add -Z/--decompress to be used with -s/--full-contents to
  decompress section contents before displaying.
* readelf: Add --extra-sym-info to be used with --symbols (currently
  prints section name of references section index).
* objcopy: Add --set-section-flags for x86_64 to include
  SHF_X86_64_LARGE.
* s390 disassembly: add target-specific disasm option 'insndesc',
  as in "objdump -M insndesc" to display an instruction description
  as comment along with the disassembly.

- Add binutils-use-less-memory.diff to be a little nicer to 32bit
  userspace and huge links.  [bsc#1216908]
- Add libzstd-devel to Requires of binutils-devel. (bsc#1215341)