This update for qemu fixes the following issues:

qemu was updated to version 8.2.5:

- For the full list of changes (from the various releases) please consult the following:
  
  * https://lore.kernel.org/qemu-devel/1718081047.648425.1238605.nullmailer@tls.msk.ru/
 
- Main changes:

  * disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
  * dockerfiles: Added 'MAKE' env variable to remaining containers
  * gitlab: Update msys2-64bit runner tags
  * gitlab: Use 'setarch -R' to workaround tsan bug
  * gitlab: Use $MAKE instead of 'make'
  * hvf: arm: Fixed encodings for ID_AA64PFR1_EL1 and debug System registers
  * hw/intc/arm_gic: Fixed handling of NS view of GICC_APR<n>
  * hw/intc/riscv_aplic: APLICs should add child earlier than realize
  * iotests: test NBD+TLS+iothread
  * qio: Inherit follow_coroutine_ctx across TLS
  * target/arm: Disable SVE extensions when SVE is disabled
  * target/i386: Fixed SSE and SSE2 feature check
  * target/i386: Fixed xsave.flat from kvm-unit-tests
  * target/i386: No single-step exception after MOV or POP SS
  * target/loongarch: Fixed a wrong print in cpu dump
  * target/riscv: Do not set mtval2 for non guest-page faults
  * target/riscv: Fixed the element agnostic function problem
  * target/riscv: Prioritize pmp errors in raise_mmu_exception()
  * target/riscv: rvv: Check single width operator for vector fp widen instructions
  * target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
  * target/riscv: rvv: Fixed Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
  * target/riscv: rvv: Removed redudant SEW checking for vector fp narrow/widen instructions
  * target/riscv: rvzicbo: Fixed CBO extension register calculation
  * target/riscv/cpu.c: Fixed Zvkb extension config
  * target/riscv/kvm: Tolerate KVM disable ext errors
  * target/riscv/kvm.c: Fixed the hart bit setting of AIA
  * ui/sdl2: Allow host to power down screen